1. Field of the Invention
The present invention relates to a column decoder array device used in semiconductor memory devices, and more particularly to a column decoder array device used in a synchronous graphic random access memory (SGRAM), in which column decoders adapted to simultaneously operate for a block write function are arranged in a laterally symmetrical manner or in a shifted manner, so as to effectively reduce the intensity of peak current.
2. Description of the Prior Art
Generally, write operations performed in SGRAM devices include a normal write operation and a block write operation. In the block write mode, an increased number of cells in a SGRAM device perform a write operation, as compared to that of the normal write mode. For instance, in the case of an 8M SGRAM (X32), it is possible to simultaneously write 32 bits in a normal write mode whereas it is possible to simultaneously write up to 256 bits in a block write mode.
In connection with such a block write operation, however, conventional column decoder array devices involve a problem in that an increase in peak current results because an increased number of column decoders operate simultaneously.